CASIS1.1: a very high dynamic range front- end electronics with integrated Cyclic ADC for calorimetry applications

In the framework of the INFN R&D projects CASIS and CASIS2, we are developing a new-concept VLSI front-end chip for the read-out of silicon calorimeters for high-energy astroparticle physics experiments. The ASIC has an input dynamic range of 52.6 pC (~ 11000 minimum ionizing particle, MIP) and features a new Charge Sensitive Amplifier (CSA) architecture, which uses a real-time automatic gain selection circuitry to switch between the input ranges of [0 divide 500 MIP] and [0 - 11000 MIP]. Following the CSA, a Correlated Double Sampling (CDS) shaper completes the front-end part. The final objective is to design and realize by 2008 a 16-channel chip with digitized outputs, which integrates one 12-bit Cyclic ADC per channel. We report on the design and tests of the second prototype (CASIS1.1) of the chip, which includes a revised and improved version of the Cyclic ADC with respect to that implemented in the first prototype (CASIS1.0).