A 2-Dimension Force-Directed Scheduling Algorithm for Register-File-Connectivity Clustered VLIW Architecture

Very long instruction word (VLIW) processors are generally implemented as clustered architectures in order to reduce delay, area and power when function units increase. However, a side effect of clustered architectures is processor performance degradation, due to additional latency and copy operations from data transfers between these clusters. Therefore, appropriate scheduling algorithms must be applied to overcome this. This paper presents a new register-file-connectivity clustered VLIW (RFCC-VLIW) architecture, in which a global register file is used to transfer data between clusters. Using the global register file, latency and copy operations can be eliminated. Additionally, the paper presents a scheduling algorithm for the RFCC-VLIW architecture. The two-dimension force-directed algorithm can assign instructions evenly to all clusters and reduce usage of ports and global registers. Experimental results show our algorithm outperforms other scheduling algorithms for clustered VLIW when targeted toward RFCC-VLIW architectures.