Fabrication Technologies for Multilayer CMOS Device

Author

Akiyama, S. ; Yoneda, M. ; Ogawa, S. ; Yoshii, N. ; Terui, Y.

Author_Institution

Advanced Device Lab., Semiconductor Research Center Matsushita Electric Industrial Co., Ltd. 3-15, Yagumonakamachi, Moriguchi-shi, Osaka 570, Japan

fYear

1985

fDate

14-16 May 1985

Firstpage

28

Lastpage

29

Abstract

Fundamental technologies required to fabricate a multilayer device were studied. Dual laser beam recrystallization method was developed to obtain homogeneous crystal quality Si islands through 5 cm Ã— 5 cm area. The planarized heat sink (PHS) structure was proposed to stack the laser recrystallized Si islands layer on the top of the lower IC. Nondoped MoSi2 was utilized as a buried interconnection to be stacking CMOS IC in an each layer, instead of a conventional A1 interconnection of CMOS. Using these fundamental process technologies for the multilayer device, the 3 level device having the different function in each active layer was fabricated and was successfully operated.

Keywords

CMOS integrated circuits; CMOS technology; Crystallization; Integrated circuit interconnections; Laser beams; Nonhomogeneous media; Optical control; Optical device fabrication; Shape control; Stacking;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Technology, 1985. Digest of Technical Papers. Symposium on

Conference_Location

Kobe, Japan

Print_ISBN

4-930813-09-3

Type

conf

Filename

4480287