DocumentCode
472650
Title
Scaled Bit Line Capacitance Analysis Using a Three-Dimensional Simulator
Author
Yoshida, Masaaki ; Takeshima, Toshio ; Takada, Masahide
Author_Institution
Microelectronics Research Laboratories, NEC Corporation 4-1-1 Miyazaki, Miyamae-ku, Kawasaki, Japan
fYear
1985
fDate
14-16 May 1985
Firstpage
66
Lastpage
67
Keywords
Analytical models; Capacitance; Circuit simulation; Degradation; Electromigration; Microelectronics; Very large scale integration; Voltage; Wires; Wiring;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Technology, 1985. Digest of Technical Papers. Symposium on
Conference_Location
Kobe, Japan
Print_ISBN
4-930813-09-3
Type
conf
Filename
4480306
Link To Document