DocumentCode
472682
Title
0.5 Micron Gate CMOS Technology Using E-Beam/Optical Mix Lithography
Author
Wang, L.K. ; Taur, Y. ; Moy, D. ; Dennard, R.H. ; Chiong, K. ; Hohn, F. ; Coane, P.J. ; Edenfeld, A. ; Carbaugh, S. ; Kenney, D. ; Schnur, S.
Author_Institution
IBM T. J. Watson Research Center, Yorktown Heights, NY 10598
fYear
1986
fDate
28-30 May 1986
Firstpage
13
Lastpage
14
Abstract
A high performance CMOS process using mix e-beam/optical lithography has been developed for VLSI applications. The 0.5 ¿m channel devices are fabricated with shallow N+ and P+ source/drain junctions. Self-aligned silicide on gate and diffusions reduces the sheet resistance to 5 ohm/sq.. The shallow retrograde N-well formed by multiple high energy phosphorous implants without a drive-in a allows the use of thin P/P+ epi for latch-up control.
Keywords
CMOS process; CMOS technology; Implants; Lithography; MOS devices; Optical films; Optical surface waves; Silicides; Very large scale integration; Writing;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Technology, 1986. Digest of Technical Papers. Symposium on
Conference_Location
San Diego, CA, USA
Type
conf
Filename
4480346
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