Title :
Submicron 3D Surface-Orientation-Optimized CMOS Technology
Author :
Kinugawa, Masaaki ; Kakumu, Masakazu ; Matsunaga, Jun´Ichi
Author_Institution :
Semiconductor Device Engineering Laboratory Toshiba Corporation 1, Komukai Toshiba-cho, Saiwai-ku, Kawasaki, 210, Japan
Keywords :
CMOS process; CMOS technology; Delay effects; MOS devices; MOSFET circuits; Parasitic capacitance; Semiconductor devices; Substrates; Transconductance; Very large scale integration;
Conference_Titel :
VLSI Technology, 1986. Digest of Technical Papers. Symposium on
Conference_Location :
San Diego, CA, USA
