Title :
Technology for a 250V Monolithic Complementary MOSFFT LSJ with N+ Buried-Layer Protected CMOS Logic
Author :
Sakamoto, Kouzou ; Okabe, Takeaki ; Kimura, Masatoshi ; Satonaka, Koichiro ; Nishimura, Takanori
Author_Institution :
Central Research Lab., Hitachi Ltd., Kokubunji, Tokyo 185
Keywords :
Breakdown voltage; CMOS logic circuits; CMOS technology; Epitaxial layers; Isolation technology; Large scale integration; Logic design; Logic devices; MOSFET circuits; Protection;
Conference_Titel :
VLSI Technology, 1986. Digest of Technical Papers. Symposium on
Conference_Location :
San Diego, CA, USA