472686

Technology for a 250V Monolithic Complementary MOSFFT LSJ with N+ Buried-Layer Protected CMOS Logic

Sakamoto, Kouzou ; Okabe, Takeaki ; Kimura, Masatoshi ; Satonaka, Koichiro ; Nishimura, Takanori

Central Research Lab., Hitachi Ltd., Kokubunji, Tokyo 185

1986

28-30 May 1986

21

22

Breakdown voltage; CMOS logic circuits; CMOS technology; Epitaxial layers; Isolation technology; Large scale integration; Logic design; Logic devices; MOSFET circuits; Protection;

English

ieee

VLSI Technology, 1986. Digest of Technical Papers. Symposium on

San Diego, CA, USA

conf

4480350