A Simple Holding Voltage Analysis for Latchup in Epitaxial CMOS

This paper presents a simple model for the holding voltage of the parasitic thyristor in epitaxial n-well CMOS. Two-dimensional device simulations of the holding point show that the region between the p+ source and the n+ source is conductivity modulated. The vertical extension of the conductivity modulated region is often greater than the tank depth. Conductivity modulation causes these regions of the p-epi and n-well to lose their separate identities. As a result the vertical hole current in both the p-epi and n-well is well represented by the majority carrier flow equations for a single transistor in high current operation. The lateral current flow is drift dominated. An expression for the holding voltage is derived based on this simplification. The analysis explains the improvement in holding voltage with increased n-to-p spacing, thinner epi, substrate backbias, shallow trench and silicided source/drain.