Title :
Shallow Trench Isolated Buried N+ FAMOS Transistors for VLSI EPROMs
Author :
Esquivel, A.L. ; Mitchell, A.T. ; Paterson, J.L. ; Tigelaar, H.L. ; Riemenschneider, B.R. ; Coffman, T.M. ; Gill, M. ; Lahiry, R. ; McElroy, D. ; Shah, P.
Author_Institution :
Semiconductor Process and Design Center-Dallas TX Texas Instruments, Incorporated MS-944, PO Box 655621, Dallas, Texas 75265, USA
Keywords :
EPROM; Electric breakdown; Etching; Instruments; Leakage current; Nonvolatile memory; Process design; Substrates; Very large scale integration; Voltage;
Conference_Titel :
VLSI Technology, 1987. Digest of Technical Papers. Symposium on
Conference_Location :
Karuizawa, Japan
