DocumentCode
472842
Title
Improved Modeling of CMOS Latch-Up and VLSI Implications
Author
Rung, R.D. ; Momose, H.
Author_Institution
Toshiba Corporation Semiconductor Device Engineering Laboratory Kawasaki, Japan
fYear
1982
fDate
1-3 Sept. 1982
Firstpage
50
Lastpage
51
Keywords
Current measurement; Electrical resistance measurement; Laboratories; Predictive models; Semiconductor device modeling; Semiconductor devices; Threshold current; Threshold voltage; Very large scale integration; Virtual manufacturing;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Technology, 1982. Digest of Technical Papers. Symposium on
Conference_Location
Oiso, Japan
Type
conf
Filename
4480573
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