472888

N- and P-Well Optimization for High Speed N-Epitaxy CMOS Circuits

Schwabe, U. ; Jacobs, E.P. ; Takacs, D. ; Bürker, U.

Siemens AG, Central Research and Development, Microelectronics, D-8000 Munich 83, Otto-Hahn-Ring 6, FRG

1983

13-15 Sept. 1983

42

43

Breakdown voltage; Circuits; Jacobian matrices; Length measurement; Parasitic capacitance; Propagation delay; Ring oscillators; Temperature; Threshold voltage; Transistors;

English

ieee

VLSI Technology, 1983. Digest of Technical Papers. Symposium on

Maui, HI, USA

4-930813-05-0

conf

4480628