DocumentCode :
472915
Title :
SiO2 Planarization by Two Step RF Bias Sputtering
Author :
Morimoto, M. ; Mogami, T. ; Okabayashi, H. ; Nagasawa, E.
Author_Institution :
Microelectronics Research Laboratories NEC Corp., Kawasaki, Japan
fYear :
1983
fDate :
13-15 Sept. 1983
Firstpage :
100
Lastpage :
101
Keywords :
Insulation; Integrated circuit interconnections; Metal-insulator structures; Planarization; Radio frequency; Sputter etching; Sputtering; Strips; Voltage; Wiring;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
VLSI Technology, 1983. Digest of Technical Papers. Symposium on
Conference_Location :
Maui, HI, USA
Print_ISBN :
4-930813-05-0
Type :
conf
Filename :
4480656
Link To Document :
https://search.ricest.ac.ir/dl/search/defaultta.aspx?DTC=49&DC=472915
بازگشت