Title :
Multilevel Metallization Technology for VLSIs
Author :
Okabayashi, Hidekazu
Author_Institution :
Microelectronics Research Labs. NEC Corp. 4-1-1 Miyazaki, Miyamae-ku, Kawasaki 213, Japan
Keywords :
Capacitance; Conductivity; Integrated circuit interconnections; Metallization; Planarization; Plasma temperature; Polyimides; Sputter etching; Sputtering; Very large scale integration;
Conference_Titel :
VLSI Technology, 1984. Digest of Technical Papers. Symposium on
Conference_Location :
San Diego, CA, USA
Print_ISBN :
4-930813-08-5