On reducing both shift and capture power for scan-based testing

Power consumption in scan-based testing is a major concern nowadays. In this paper, we present a new X-fllling technique to reduce both shift power and capture power during scan tests, namely LSC-filling. The basic idea is to use as few as possible X-bits to keep the capture power under the peak power limit of the circuit under test (CUT), while using the remaining X-bits to reduce the shift power to cut down the CUT´s average power consumption during scan tests as much as possible. In addition, by carefully selecting the X-filling order, our X-filling technique is able to achieve lower capture power when compared to existing methods. Experimental results on ISCAS´89 benchmark circuits show the effectiveness of the proposed methodology.