A Simple and Accurate Model of Input capacitance for Power Estimation in CMOS logic

In this paper, an analytical model of the input capacitance of nanometer CMOS gates is proposed. The model accounts for the non-linear behavior of the gate capacitance in sub-100 nm technologies, and allows to gain an insight into the dependence on the supply voltage. Its application to power modeling is explicitly dealt with. The model is fully analytical hence no look-up tables are needed to implement it. Moreover, it is simple and does not require simulations or fitting parameters, thus it is well suited for efficient gate-level modeling in automated design. The model is shown to agree well with circuit simulation results, as an error as low as a few percentage points is found for a 90-nm CMOS technology.