DocumentCode
474462
Title
Model checking based analysis of end-to-end latency in embedded, real-time systems with clock drifts
Author
Mohalik, Swarup ; Rajeev, A.C. ; Dixit, Manoj G. ; Ramesh, S. ; Vijay Suman, P. ; Pandya, Paritosh K. ; Jiang, Shengbing
Author_Institution
Gen. Motors India Sci. Lab., Bangalore
fYear
2008
fDate
8-13 June 2008
Firstpage
296
Lastpage
299
Abstract
End-to-end latency of messages is an important design parameter that needs to be within specified bounds for the correct functioning of distributed real-time control systems. In this paper we give a formal definition of end-to-end latency, and use this as the basis for checking whether a stipulated deadline is violated within a bounded time. For unbounded verification, we model the system as a set of communicating timed automata, and perform reachability analysis. The proposed method takes into account the drift of clocks which is shown to affect the latency appreciably. The method has been tested on a medium sized automotive example.
Keywords
automata theory; embedded systems; formal verification; message passing; reachability analysis; clock drifts; distributed real-time control systems; end-to-end latency; model checking based analysis; reachability analysis; real-time systems; timed automata; unbounded verification; Automata; Automatic control; Automotive engineering; Clocks; Control systems; Delay; Distributed control; Reachability analysis; Real time systems; Testing; Clock drifts; End-to-end latency; Model checking; Task chain; Timed Automata;
fLanguage
English
Publisher
ieee
Conference_Titel
Design Automation Conference, 2008. DAC 2008. 45th ACM/IEEE
Conference_Location
Anaheim, CA
ISSN
0738-100X
Print_ISBN
978-1-60558-115-6
Type
conf
Filename
4555826
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