Miss reduction in embedded processors through dynamic, power-friendly cache design

Author

Bournoutian, Garo ; Orailoglu, Alex

Author_Institution

Univ. of California, La Jolla, CA

fYear

2008

fDate

8-13 June 2008

Firstpage

304

Lastpage

309

Abstract

Today, embedded processors are expected to be able to run complex, algorithm-heavy applications that were originally designed and coded for general-purpose processors. As a result, traditional methods for addressing performance and determinism become inadequate. This paper explores a new data cache design for use in modern high-performance embedded processors that will dynamically improve execution time, power efficiency, and determinism within the system. The simulation results show significant improvement in cache miss ratios and reduction in power consumption of approximately 30% and 15%, respectively.

Keywords

cache storage; embedded systems; memory architecture; microprocessor chips; cache miss ratios; execution time; high-performance embedded processors; power consumption reduction; power efficiency; power-friendly data cache design; Algorithm design and analysis; Cellular phones; Computational modeling; Embedded computing; Embedded system; Energy consumption; Hardware; Permission; Pervasive computing; Video codecs; data cache; dynamic associativity; embedded processors; multi-core;

fLanguage

English

Publisher

ieee

Conference_Titel

Design Automation Conference, 2008. DAC 2008. 45th ACM/IEEE

Conference_Location

Anaheim, CA

ISSN

0738-100X

Print_ISBN

978-1-60558-115-6

Type

conf

Filename

4555828