How to let instruction set processor beat ASIC for low power wireless baseband implementation: A system level approach

In this paper, we argue that we can potentially let ISP based SDR baseband implementation beat dedicated ASIC for average energy efficiency. We propose solutions at system-level with software oriented and algorithmic techniques. The key idea is leveraging the advantage (programmability) of ISP to compensate its disadvantages (lower MOPS/mW). A structurally complex agile baseband implementation on ISP can exploit the inherent dynamics in wireless communication systems, resulting in substantial reductions of active instructions and memory accesses.