Towards a more physical approach to gate modeling for timing, noise, and power

Timing, noise, and power analysis have historically relied on high level, black-box, non-physical logic library models. Moreover, these models were of a look-up type, i.e. pre- characterized for practically all the possible environments in which they would be eventually used. The evolution of the VLSI technology towards nanometer sized features made this characterization methodology impractical. Increasingly, the space of all possible environments grew too rich to be fully covered during characterization. In the past decade, the so-called effective capacitance was introduced to provide some analysis capability to gate models, i.e., the ability to evaluate in the presence of RC loads, although characterized with capacitive loads only. In current and future VLSI technologies, such simple extensions no longer provide the required accuracy. Increasingly, models of logic gates must retain elements of the electrical behavior of the circuit in order to provide accurate timing, noise, and power information. This poses a new challenge on the analysis algorithms, now required to handle an enhanced level of detail in modeling without significantly degrading the overall efficiency of the application.