Title :
Challenges in gate level modeling for delay and SI at 65nm and below
Author :
Keller, Igor ; King Ho Tarn ; Kariat, Vinod
Author_Institution :
Cadence Design Syst., Inc., San Jose, CA
Abstract :
In this paper we review the prior art and recent advances in the area of standard cell modeling for delay and noise analyses, suggest a taxonomy of different cell models, and discuss their strengths and weaknesses. We also discuss challenges in cell modeling for delay and noise analyses arising in new submicron process nodes.
Keywords :
delays; integrated circuit modelling; integrated circuit noise; logic gates; delay analyses; gate level modeling; noise analyses; size 65 nm; standard cell modeling; submicron process nodes; CMOS technology; Circuit simulation; Crosstalk; Delay; Integrated circuit modeling; Permission; Semiconductor device measurement; Semiconductor device modeling; Silicon; Timing; Delay Calculation; Gate Characterization; Gate Modeling;
Conference_Titel :
Design Automation Conference, 2008. DAC 2008. 45th ACM/IEEE
Conference_Location :
Anaheim, CA
Print_ISBN :
978-1-60558-115-6
