Title :
Automatic synthesis of clock gating logic with controlled netlist perturbation
Author_Institution :
Univ. of California, Berkeley, CA
Abstract :
Clock gating is the insertion of combinational logic along the clock path to prevent the unnecessary switching of registers and reduce dynamic power consumption. The conditions under which the transition of a register may be safely blocked can either be explicitly specified by the designer or detected automatically. We introduce a new method for automatically synthesizing these conditions in a way that minimizes netlist perturbation and is both timing- and physical-aware. Our automatic method is also scalable, utilizing simulation and satisfiability tests and necessitating no symbolic representation. On a set of benchmarks, our technique successfully reduces the dynamic clock power by 14.5% on average. Furthermore, we demonstrate how to apply a straightforward logic simplification to utilize resulting don´t cares and reduce the logic by 7.0% on average.
Keywords :
clocks; logic design; logic gates; perturbation theory; automatic synthesis; clock gating logic; dynamic clock power; netlist perturbation; registers; Automatic control; Automatic logic units; Circuits; Clocks; Cost function; Energy consumption; Network synthesis; Registers; Signal synthesis; Switches; Clock Gating; Dynamic Power; Logic Optimization; Low Power;
Conference_Titel :
Design Automation Conference, 2008. DAC 2008. 45th ACM/IEEE
Conference_Location :
Anaheim, CA
Print_ISBN :
978-1-60558-115-6