• DocumentCode
    474555
  • Title

    Towards acceleration of fault simulation using Graphics Processing Units

  • Author

    Gulati, Kanupriya ; Khatri, Sunil P.

  • Author_Institution
    Dept. of ECE, Texas A&M Univ., College Station, TX
  • fYear
    2008
  • fDate
    8-13 June 2008
  • Firstpage
    822
  • Lastpage
    827
  • Abstract
    In this paper, we explore the implementation of fault simulation on a graphics processing unit (GPU). In particular, we implement a fault simulator that exploits thread level parallelism. Fault simulation is inherently parallelizable, and the large number of threads that can be computed in parallel on a GPU results in a natural fit for the problem of fault simulation. Our implementation fault- simulates all the gates in a particular level of a circuit, including good and faulty circuit simulations, for all patterns, in parallel. Since GPUs have an extremely large memory bandwidth, we implement each of our fault simulation threads (which execute in parallel with no data dependencies) using memory lookup. Fault injection is also done along with gate evaluation, with each thread using a different fault injection mask. All threads compute identical instructions, but on different data, as required by the Single Instruction Multiple Data (SIMD) programming semantics of the GPU. Our results, implemented on a NVIDIA GeForce GTX 8800 GPU card, indicate that our approach is on average 35 x faster when compared to a commercial fault simulation engine. With the recently announced Tesla GPU servers housing up to eight GPUs, our approach would be potentially 238 times faster. The correctness of the GPU based fault simulator has been verified by comparing its result with a CPU based fault simulator.
  • Keywords
    circuit CAD; computer graphic equipment; fault simulation; integrated circuit testing; parallel processing; fault injection; fault simulation; graphics processing units; memory lookup; single instruction multiple data programming; thread level parallelism; Acceleration; Bandwidth; Circuit faults; Circuit simulation; Computational modeling; Computer aided instruction; Concurrent computing; Graphics; Parallel processing; Yarn; Fault Simulation; Graphics Processing Units;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Design Automation Conference, 2008. DAC 2008. 45th ACM/IEEE
  • Conference_Location
    Anaheim, CA
  • ISSN
    0738-100X
  • Print_ISBN
    978-1-60558-115-6
  • Type

    conf

  • Filename
    4555933