Noise optimization of fast charge sensitive amplifier in submicron technology for low power application

Charge sensitive amplifiers (CSA) are widely used in processing the signals from particle and X-ray detectors in different imaging techniques in medicine, biology, material science or physics. The requirements for imaging techniques are going in the direction of dense array of sensors, with fast and low power readout electronics designed in submicron CMOS technology. One of the critical parameters of the front-end electronics is its low noise performance, which for given application depends on many factors: sensor parameters, readout electronics architecture, technology used and power budget. For CSA the dominant noise contribution comes from input MOS transistor which often operates in weak or moderate inversion region due to strict power limitation. Using the EKV MOS transistor model one can take into account all important transistors parameters during noise optimisation process and calculate the optimum transistor dimensions and the minimum noise level for given detector - readout electronics configuration. We present both the methodology of noise optimisation and the results of noise simulation for low power, high density array of CSA design in submicron technology for application in large matrix of pixel hybrid detectors.