A 9-bit 1GS/S CMOS folding ADC implementation using TIQ based flash ADC cores

The purpose of this work is to employ the so-called Threshold Inverter Quantization (TIQ) technique in traditional CMOS folding ADC architectures. It also has a novel approach when multiplexing the appropriate folded signals into the fine flash part of the converter. The simulation results include 1MHz analogue input bandwidth, 1 Gs/s sampling rate using AMS-HIT KIT design library for 0.35μ H35B4 CMOS process model parameters. The analogue range is 1.7V, power supply is 3.3V, and maximum power consumption is 375mW. This paper also focuses on practical design considerations of the analogue pre-processing unit in folding ADCs.