A current-mode filter for wireless systems in 65 nm CMOS technology

A 3^rd-order current-mode Butterworth low-pass filter is proposed, which is based on current-mode integrators. A new current-mode integrator is realized that offers an area-saving chip design. The low-pass filter is designed and realized in 65nm low-power CMOS technology and needs 215μmx221μm chip area. The power consumption is 12mW at a supply voltage of 1.2 V . The cut-off frequency of the filter is switchable between 1MHz and 4MHz. The measurement of noise and total harmonic distortion result in a dynamic range of 77.3 dB and 71.3 dB for 1MHz and 4MHz, respectively. The filter is designed to be part of a transmit path in a Software Defined Radio (SDR) system on chip that fits for a couple of wireless applications.