A low-power closed-loop duty-cycle correction integrated circuit

A new low-power closed-loop 50% duty-cycle correction (DCC) circuit is proposed. The designed circuit is based on pulsewidth control loop circuit by adding an SR-latch unit to generate 50% duty-cycle. The output clock has a fixed-delay rising-edge. When designed with a 0.18-μm CMOS technology and supply voltage of 1.8 V, the output duty-cycle is adjusted to 50 ± 0.7% for the acceptable duty-cycle of the input duty-cycle ranges from 30% to 60% at 1 GHz clock frequency. The power consumption is reduced to 1/8 (i.e. 87% reduction) and area consumption is reduced to almost 1/4 (i.e. 75% reduction) respect to the conventional digital DCC circuit.