Title :
Error reduced Delta Sigma Modulator by improved memory cell for speech signal processing application
Author :
Kuo, J.R. ; Wu, H.C. ; Shiau, M.-S. ; Liu, D.-G.
Author_Institution :
Feng Chia University, CHINA
Abstract :
This paper presents a error reduced second-order Sigma-Delta Modulator (SDM) with the improved switched-current memory cell. The improved memory cell consists of Ground Gate Voltage Amplifier (GGA) and the basic memory cell with reduced charge injection error. The charge injection error in basic memory cell is reduced due to the technique of current source replication. The improved memory cell circuit has the following improvement. Offset error, linear gain error, and total harmonic distortion are reduced significantly. The SDM for speech signal processing application was simulated with TSMC 0.35μm 2P4M standard CMOS process technology and a single 3.3V power supply.. Simulation results show that the SDM has maximum signal-to-noise and distortion ratio of 68dB, power consumption of 9.77mW.
Keywords :
CMOS process; CMOS technology; Circuit simulation; Delta-sigma modulation; Gain; Power supplies; Signal processing; Speech processing; Total harmonic distortion; Voltage; Clock-feedthrough; Current memory cell; Sigma-Delta modulator; Switched-current;
Conference_Titel :
Mixed Design of Integrated Circuits and Systems, 2008. MIXDES 2008. 15th International Conference on
Conference_Location :
Poznan, Poland
Print_ISBN :
978-83-922632-7-2
Electronic_ISBN :
978-83-922632-8-9
