Trade-off between on-chip decoupling capacitor and error tolerance in digital IC’S under noisy environment

Modern VLSI systems are continuously increasing its operating frequency, device density and parallelism which increase the magnitude and slew rate of transient demanded current. These trends in combination with the parasitic inductance of IC package and resistive nature of Power Delivery Network (PDN) results on power-to-ground voltage fluctuations causing timing violations on digital circuits. As technology advances the operating voltage levels are reduced aggravating these problems as noise does not scale with technology. The most commonly used solution is to incorporate on-chip decoupling capacitors to the PDN to keep the noise within a tolerance margin ensuring circuits functionality. However, the cost of this technique in area and leakage current increases with technology node. In this paper the trade-off between reducing on-chip decoupling capacitors size, its consequence on voltage level fluctuations and error rate due to timing violations is analyzed for incoming technologies.