DocumentCode
475488
Title
FPGA implementation of a lossless to lossy bitonal image compression system
Author
Savakis, A. ; Lukowiak, M. ; Pyle, J.
Author_Institution
Rochester Institute of Technology, USA
fYear
2008
fDate
19-21 June 2008
Firstpage
563
Lastpage
566
Abstract
This paper presents an FPGA implementation of a lossless to lossy image compression system that incorporates region of interest processing. Block Arithmetic Coder Image Compression is combined with Low-Latency Greedy Flipping Utilizing Forgetful Error Diffusion for loss introduction. The system allows for perfect quality, associated with lossless compression, or three levels of reduced image quality, high, medium and low, associated with various levels of loss introduction. Region of interest processing can be incorporated by adjusting the system parameters for maximum visual benefit.
Keywords
Arithmetic; Code standards; Encoding; Field programmable gate arrays; Hardware; Image coding; Image generation; Image quality; Microelectronics; Pixel; Block arithmetic coder; FPGA implementation; Near lossless bitonal compression; Region of interest processing;
fLanguage
English
Publisher
iet
Conference_Titel
Mixed Design of Integrated Circuits and Systems, 2008. MIXDES 2008. 15th International Conference on
Conference_Location
Poznan, Poland
Print_ISBN
978-83-922632-7-2
Electronic_ISBN
978-83-922632-8-9
Type
conf
Filename
4600984
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