Parallel Dual-Accumulator based Mel Frequency Cepstral Coefficient for speech recognition

This paper proposed a parallel dual-accumulator (PDA) based Mel frequency cepstral coefficient (MFCC). MFCC is an important feature in speech recognition. To implement this MFCC, we adopt the PDA architecture to reduce the calculation of weighted energy spectrum. In addition, we minimize the look-up table for logarithm operation. Finally, the resource sharing method is adopted into our design. Hence, compared with Wang et al. [5], the proposed architecture can reduce not only the computation cycles but also the chip size.