Implementation of matrix-type FDTD algorithm on a graphics accelerator

Author

Dziekonski, Adam ; Sypek, Piotr ; Kulas, Lukasz ; Mrozowski, Michal

Author_Institution

Dept. of Microwave & Antenna Eng., Gdansk Univ. of Technol., Gdansk

fYear

2008

fDate

19-21 May 2008

Firstpage

1

Lastpage

4

Abstract

This paper presents initial conclusions concerning the implementation of matrix-type FDTD algorithm on a low cost graphics accelerator (Nvidia GeForce GT 512 MB, 1.188 GHz) in CUDA (compute unified device architecture). Authors of this article pose a question as to whether using the graphics accelerator based on SIMD architecture (single instruction, multiple data) is reasonable in programming a matrix-type FDTD algorithm, then results of tests meant to compare the efficiency of sequential and parallel implementation are presented.

Keywords

computer graphic equipment; finite difference time-domain analysis; mathematics computing; parallel processing; CUDA; SIMD architecture; compute unified device architecture; graphics accelerator; matrix-type FDTD algorithm; single instruction multiple data; Acceleration; Biology computing; Central Processing Unit; Computational electromagnetics; Computer architecture; Computer graphics; Finite difference methods; Signal processing algorithms; Sparse matrices; Time domain analysis;

fLanguage

English

Publisher

ieee

Conference_Titel

Microwaves, Radar and Wireless Communications, 2008. MIKON 2008. 17th International Conference on

Conference_Location

Wroclaw

Print_ISBN

978-83-906662-8-0

Type

conf

Filename

4630162