Parallel architecture for decoding LDPC Codes on high speed communication systems

Author

Morero, Damian A. ; Corral-Briones, Graciela ; Hueda, Mario R.

Author_Institution

Digital Commun. Res. Lab., Nat. Univ. of Cordoba, Cordoba

fYear

2008

fDate

18-19 Sept. 2008

Firstpage

107

Lastpage

110

Abstract

This paper presents a novel parallel architecture for decoding LDPC codes. The proposed architecture has low memory and interconnection requirements, becoming attractive for high speed applications such as fiber optic communications and high density magnetic recording. As an example, the implementation on an FPGA of a TPC/SPC code using the proposed architecture will also be described.

Keywords

field programmable gate arrays; iterative decoding; parallel architectures; parity check codes; product codes; turbo codes; FPGA implementation; LDPC codes decoding; TPC/SPC code; fiber optic communications; high density magnetic recording; high speed communication systems; iterative decoders; low density parity check codes; parallel architecture; single parity check code; turbo product code; Digital communication; Field programmable gate arrays; Integrated circuit interconnections; Iterative decoding; Laboratories; Memory architecture; Optical fiber communication; Paper technology; Parallel architectures; Parity check codes;

fLanguage

English

Publisher

ieee

Conference_Titel

Micro-Nanoelectronics, Technology and Applications, 2008. EAMTA 2008. Argentine School of

Conference_Location

Buenos Aires

Print_ISBN

978-987-655-003-1

Electronic_ISBN

978-987-655-003-1

Type

conf

Filename

4638987