DocumentCode
478833
Title
Resource mapping and scheduling for heterogeneous network processor systems
Author
Liang Yang ; Gohad, T. ; Ghosh, P. ; Sinha, D. ; Sen, A. ; Richa, A.
Author_Institution
Dept. of Comput. Sci. & Eng., Arizona State Univ., Tempe, AZ
fYear
2005
fDate
26-28 Oct. 2005
Firstpage
19
Lastpage
28
Abstract
Task to resource mapping problems are encountered during (i) hardware-software co-design and (ii) performance optimization of Network Processor systems. The goal of the first problem is to find the task to resource mapping that minimizes the design cost subject to all design constraints. The goal of the second problem is to find the mapping that maximizes the performance, subject to all architectural constraints. To meet the design goals in performance, it may be necessary to allow multiple packets to be inside the system at any given instance of time and this may give rise to the resource contention between packets. In this paper, a Randomized Rounding (RR) based solution is presented for the task to resource mapping and scheduling problem. We also proposed two techniques to detect and eliminate the resource contention. We evaluate the efficacy of our RR approach through extensive simulation. The simulation results demonstrate that this approach produces near optimal solutions in almost all instances of the problem in a fraction of time needed to find the optimal solution. The quality of the solution produced by this approach is also better than often used list scheduling algorithm for task to resource mapping problem. Finally, we demonstrate with a case study, the results of a Network Processor design and scheduling problem using our techniques.
Keywords
hardware-software codesign; resource allocation; scheduling; hardware-software co-design; heterogeneous network processor systems; randomized rounding; resource mapping; resource scheduling; task mapping; Computer science; Costs; Cryptography; Design engineering; Network address translation; Optimization; Permission; Processor scheduling; Software performance; Virtual private networks; HW-SW partitioning; codesign; network processor; randomized rounding;
fLanguage
English
Publisher
ieee
Conference_Titel
Architecture for networking and communications systems, 2005. ANCS 2005. Symposium on
Conference_Location
Princeton, NJ
Print_ISBN
978-1-59593-082-8
Type
conf
Filename
4675262
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