Title :
Minitaur, an Event-Driven FPGA-Based Spiking Network Accelerator
Author :
Neil, Dan ; Shih-Chii Liu
Author_Institution :
Inst. of Neuroinf., Univ. of Zurich, Zürich, Switzerland
Abstract :
Current neural networks are accumulating accolades for their performance on a variety of real-world computational tasks including recognition, classification, regression, and prediction, yet there are few scalable architectures that have emerged to address the challenges posed by their computation. This paper introduces Minitaur, an event-driven neural network accelerator, which is designed for low power and high performance. As an field-programmable gate array-based system, it can be integrated into existing robotics or it can offload computationally expensive neural network tasks from the CPU. The version presented here implements a spiking deep network which achieves 19 million postsynaptic currents per second on 1.5 W of power and supports up to 65 K neurons per board. The system records 92% accuracy on the MNIST handwritten digit classification and 71% accuracy on the 20 newsgroups classification data set. Due to its event-driven nature, it allows for trading off between accuracy and latency.
Keywords :
field programmable gate arrays; neural nets; CPU; MNIST handwritten digit classification; Minitaur; event-driven FPGA; event-driven neural network accelerator; field-programmable gate array-based system; neural networks; newsgroups classification data; robotics; spiking deep network; spiking network accelerator; Biological neural networks; Clocks; Computer architecture; Field programmable gate arrays; Mathematical model; Neurons; Performance evaluation; Deep belief networks; field programmable arrays; machine learning; neural networks; restricted Boltzmann machines; spiking neural networks;
Journal_Title :
Very Large Scale Integration (VLSI) Systems, IEEE Transactions on
DOI :
10.1109/TVLSI.2013.2294916