Total Ionizing Dose Effects Mitigation Strategy for Nanoscaled FDSOI Technologies

We propose a TID effect hardening strategy for nanoscaled ultra-thin BOX and body SOI technologies. Experiments performed on NMOS and PMOS transistors demonstrate that TID effects can be mitigated by applying a dynamic back-bias technique. These data are used to calibrate the back-bias that has to be applied on UTSOI transistors to efficiently mitigate TID-induced effects. Elementary circuit cells made of inverters are then modeled using dedicated mixed TCAD calculations in order to validate the proof of concept of this hardening strategy at circuit level. Finally, results obtained on Ultra-Thin BOX devices typical of future FDSOI technologies show that the proposed hardening strategy efficiency increases with BOX thinning and then with technology downscaling.