FPGA-Based Co-processor for Singular Value Array Reconciliation Tomography

We present an FPGA-based co-processor for accelerating computations associated with Singular Value Array Reconciliation Tomography (SART), a recently developed method for RF source localization. The co-processor allows this relatively complex computational task to be performed using less hardware and less power than would be required by a microprocessor-based computing cluster with comparable throughput and accuracy. The architecture exploits parallelism of the SART algorithm at many levels in order to efficiently map it into the FPGA platform. The system has been developed in VHDL, and implemented on a Virtex-4 SX55 FPGA. Compared to a Pentium 4 CPU running at 3 GHz, use of the co-processor system provides a speed-up of about 6 times for the current signal matrix size of 128-by-16. Greater speed-ups will be obtained when larger matrices are processed because the co-processor reduces the complexity of a m-by-n SVD from O(mn²), to O(mn). Even larger speed-ups may be obtained by using multiple devices in parallel. The system is capable of computing the SART metric to an accuracy of about -145 dB (0.2 ppm) with respect to its true value. This level of accuracy, which is better than that obtained using single precision floating point arithmetic, allows even relatively weak signals to make a meaningful contribution to the final SART solution.