Multi-mode compliant digital enhanced transmitter architectures in nano-scale CMOS

This paper treats two different transmitter concepts both enhanced by highly flexible and generic digital architectures. The first investigated transmitter is based on a state-of-the-art direct up-conversion transmitter extended with a digital front end and the second concept is a polar transmitter (PT). Crucial part is to mitigate radio frequency (RF) impairments by the means of digital compensation techniques, e.g. direct current (DC) and I/Q gain imbalance and digital predistortion. Both transmitter architectures are multi-mode compliant and shall support LTE, UMTS, CDMA2000, and GSM. Each transmitter concept utilizes a highly reconfigurable all digital phase locked loop (ADPLL). In the case of the direct up-conversion transmitter the ADPLL is used for RF synthesis and in the case of the PT it is used as phase modulator. Furthermore, measurement results for RF synthesis, realized by an ADPLL in a 130 nm complementary metal oxide semiconductor (CMOS) process technology, will be presented.