DocumentCode :
481573
Title :
A 19.1-dBm fully-integrated 24 GHz power amplifier using 0.18-μm CMOS technology
Author :
Kuo, Jing-Lin ; Tsai, Zuo-Min ; Wang, Huei
Author_Institution :
Dept. of Electr. Eng. & Grad. Inst. of Commun. Eng., Nat. Taiwan Univ., Taipei
fYear :
2008
fDate :
27-28 Oct. 2008
Firstpage :
234
Lastpage :
237
Abstract :
A 24 GHz, 19.1 dBm fully-integrated power amplifiers (PA) was designed and fabricated in the 0.18-mum deep n-well (DNW) CMOS technology. This power amplifier is a 2-stage design using cascode RF NMOS configuration and has a maximum measured output power of 19.1 dBm, an OP1dB of 13.3 dBm, a power added efficiency (PAE) of 15.6%, and a linear gain of 18.8 dB when VDD and DNW are both biased at 3.6 V. The chip size is only 0.56 times 0.58 mm2. To the authorpsilas knowledge, this PA demonstrates the highest output power of +19.1 dBm among the reported PAs above 15 GHz in CMOS processes.
Keywords :
CMOS integrated circuits; integrated circuit design; power amplifiers; power integrated circuits; CMOS technology; cascode RF NMOS configuration; deep n-well; fully itegrated power amplifier; power added efficiency; size 0.18 mum; CMOS technology; Gain measurement; MOS devices; Power amplifiers; Power generation; Power measurement; Radio frequency; Radiofrequency amplifiers; Semiconductor device measurement; Size measurement;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Wireless Technology, 2008. EuWiT 2008. European Conference on
Conference_Location :
Amsterdam
Print_ISBN :
978-2-87487-008-8
Type :
conf
Filename :
4753850
Link To Document :
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