AC drive system on chip controller with non-linearity errors compensation

This paper presents the implementation of a system on chip (SoC) controller for a synchronous machine using a fusion field programmable gate array (FPGA). This component integrates, in addition to an FPGA matrix, analog peripherals such as, analog to digital converter (ADC), analog prescalers and an analog multiplexer for multi-channel conversion. Thus, in such application and in order to improve the control quality, a compensation of the ADC non-linearity error is achieved. Moreover, sampling synchronization error (SSE) compensation is implemented in order to minimize the impact of the serialized conversion process. Besides this ADC errors compensation, and always in perspective to improve the control quality, the voltage source inverter (VSI) non-linearity error compensation is implemented. This VSI error is mainly due to the introduced dead time, to power switches turn-on/off delays and also to the voltage drops. Simulations and experimental results are given to illustrate the efficiency of the developed compensation methods.