DocumentCode :
483578
Title :
A simplified addition operation Log-SPA LDPC decoder
Author :
Yang, Po-Hui ; Chen, Jung-Chieh ; Chan, Ya-ring ; Lin, Ming-Yu
Author_Institution :
Dept. of Electron. Eng., Nat. Yunlin Univ. of Sci.&Technol.
fYear :
2008
fDate :
14-16 Oct. 2008
Firstpage :
1
Lastpage :
4
Abstract :
A low hardware cost low-density parity-check (LDPC) decoder is presented in this paper. Using logical OR operation in the check nodes for the log sum-product algorithm (Log-SPA), we propose a new architecture for updating the check nodes messages. Synthesized and numerical results show that the proposed architecture achieves up to 21% total hardware reduction with fair BER performance when compared with the traditional log-SPA decoder. Moreover, the proposed decoder also outperforms the simplest known sign-min architecture in terms of hardware complexity and BER performance.
Keywords :
error statistics; parity check codes; product codes; BER performance; addition operation; bit error rate; log sum-product algorithm; log-SPA LDPC decoder; logical OR operation; low-density parity-check decoder; Bit error rate; Costs; Decoding; Hardware; Joining processes; Logic gates; Mice; Parity check codes; Sum product algorithm; Very large scale integration; LDPC decoding; Sum-product algorithm;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Communications, 2008. APCC 2008. 14th Asia-Pacific Conference on
Conference_Location :
Tokyo
Print_ISBN :
978-4-88552-232-1
Electronic_ISBN :
978-4-88552-231-4
Type :
conf
Filename :
4773743
Link To Document :
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