A Floating-point Coprocessor Configured by a FPGA in a Digital Platform Based on Fixed-point DSP for Power Electronics

A configurable floating-point coprocessor by a FPGA is designed to enhance the computational capability of the digital platform based on the fixed-point DSP, with which the platform will be competent to implement intensively computational tasks. Detailed design procedures of the coprocessor are presented. A new division algorithm is proposed by combining the lookup-table algorithm and multiplicative algorithm in order to reduce the number of LEs (Logic Element in FPGA) and latency. Error analysis of the proposed algorithm shows that the maximum absolute approximate error is less than 2ulp (Unit in Last Place). The coprocessor speed can reach up to 25 MFLOP (Million Floating-point Operations). FFT algorithm is adopted to test the computational efficiency of the floating-point units. Experimental results show the computation time by FPU is five times less than that of DSP algorithms