TAM optimization and test scheduling for SoC based on zigzag design flow

Traditional SoC design-for-test (DFT) flow involves the sequence of determining detailed test architecture, choosing the approach of test scheduling and implementing core test. Such procedure may produce the issues of physical realizability and workability. To conquer the inefficiency of the past test flow, a new test flow whose shape is like letter Z, is presented. The Z design flow consists of proposing conceptual test architecture with uncertain test access mechanism(TAM) width, deciding the test scheduling to satisfy the required weighted test cost(WTC), then defining the deterministic test architecture and executing the core test. To better make tradeoffs between test time and hardware overhead during the Z design flow, a new test scheduling approach is explored. The verification result demonstrates the efficiency and usefulness of the proposed technique. The optimal WTC for benchmark circuit using the proposed algorithm is 55% of the average WTC.