Analysis of the Performance, Power, and Noise Characteristics of a CMOS Image Sensor With 3-D Integrated Image Compression Unit

This paper investigates the design of logarithmic CMOS image sensor with 3-D integrated image compression unit. The image sensor consists of a pixel array, column circuits, an array of analog-to-digital converters, a frame memory (image buffer) array, and a signal processing unit for image compression. This paper analyzes the correlation between the power dissipation in the image compression unit and the spatial noise characteristics of the photodiode array in the 3-D image sensor. The coupled power, performance, thermal, and noise analysis is performed considering 180-nm CMOS technology. The coupled analysis shows that, due to die-to-die thermal coupling, 3-D stacking of the image compression unit, although provides for better energy efficiency, results in a strong interaction between image quality, desired image throughput, and environmental factors, such as lighting conditions or available channel bandwidth.