An Architecture for a Multiple Function Speech Processor

A study of the feasibility of realizing a compact, multiple function speech processor is presented in this paper. The processor is required to accommodate either a 2400 bps Linear Predictive Coder, a 9600 bps Adaptive Predictive Coder, or a wireline modem at one of the corresponding data rates. This capability is obtained by designing a speech processing board whose function can be customized to any single task by inserting the appropriate set of PROMs. The concurrent goals of compactness and processor sophistication are achieved by augmenting a digital signal processing integrated circuit chip with external support hardware. An example of such an implementation, which uses the Fujitsu MB8764 as the computation engine, is presented. Because the Fujitsu chip lacks a hardware interrupt and has a limited memory address space, special purpose hardware was designed to implement the interrupt capability externally and to expand both program and data memory using a paging scheme. A detailed study of the design indicates that a compact realization of the multiple function processor can be realized using commercially available hardware and one readily designed custom integrated circuit.