Multi-Channel Viterbi Decoder LSI Development

A multi-channel Viterbi decoder LSI chip has been developed at Harris Corporation, GCSD. This chip, targeted for implementation in SAJI-4 technology, can service up to 50 channels of encoded data at an aggregate channel symbol rate up to 120 KHz. The LSI design includes all decoder functions on-chip except those functions requiring large amounts of memory such as path metric and trellis bit storage. It also provides the capability for external or internal symbol synchronization and includes provisions for handling block formatted data. This paper discusses the development of the CMOS LSI design. Topics include system considerations, design trade-offs and methodologies used for simulation, verification, and testing of the multi-channel Viterbi decoder LSI chip.