Title :
Matched filter implementation on FPGA for integrand code using a real-valued shift-orthogonal finite-lenght sequence
Author :
Matsumoto, Takahiro ; Matsufuji, Shinya
Author_Institution :
Grad. Sch. of Sci. & Eng., Yamaguchi Univ., Ube
Abstract :
In this paper, we proposed the compact construction of a matched filter for integrand code, which do not require the high-rate clock pulse in two-valued PWM (pulse width modulation) code, using a real-valued shift-orthogonal finite-length sequence, which has a sharp a periodic autocorrelation function with zero sidelobes except at left and right shift-ends. This matched filters is implemented on a field programmable gate array (FPGA) corresponding to 400,000 gates. A proposed matched filter for the sequence of length 129 can be constructed by the circuit scale of about 47% compared with conventional filter.
Keywords :
field programmable gate arrays; matched filters; pulse width modulation; FPGA; autocorrelation function; field programmable gate array; integrand code; matched filter; pulse width modulation; shift-orthogonal finite-length sequence; Autocorrelation; Circuits; Clocks; Field programmable gate arrays; Matched filters; Modulation coding; Programmable logic arrays; Pulse width modulation; Space vector pulse width modulation; Spread spectrum radar; field programmable gate array; finite length sequence; integrand code; matched filter; real-valued sequence;
Conference_Titel :
Advanced Communication Technology, 2009. ICACT 2009. 11th International Conference on
Conference_Location :
Phoenix Park
Print_ISBN :
978-89-5519-138-7
Electronic_ISBN :
1738-9445