Performance and wake-up schedule optimization of power gating design

Leakage power has become a major concern in mobile device and power gating is a very popular technique to reduce the leakage power. In this paper, we discuss two important optimization issues in power gating designs. One is the sizing problem of the sleep transistors which are the trade-off between the size and IR drop noise in the power gating designs. We also discuss the wake-up schedule optimization and propose efficient wake-up schedule for a power gating design. Our experimental results are very encouraging.