Parametric yield-aware sign-off flow in 65/45nm

Due to the increased random variations in nanometer silicon process technology as well as voltage and temperature variations, it is very hard to guarantee performance characteristics with traditional corner-based timing analysis method. The variations, together with the issues like crosstalk and jitter, make it difficult to get a good silicon correlation with simulation and to meet target performance. The advent of SSTA(Statistical Static Timing Analysis) gave the opportunity to solve this problem. This paper proposes a parametric yield-aware sign-off environment based on the SSTA technology. With the proposed environment, it is possible to accurately predict the yield data with sigma level at a given target performance. This environment includes a unique methodology to get silicon correlation from various measurement data and to implement a chip with a given sigma level.