Communication modeling for system-level design

Multiprocessor systems-on-chip (MPSoCs) are emerging as a popular SoC design platform. However, major challenges arise from nonscaling global wire delay and from the reuse of intellectual properties (IPs) from different vendors to meet tight time-to-market constraints. Designing the appropriate communication fabrics for such heterogeneous systems becomes a challenging task. In this paper, we present accurate delay, power, and area models for bus-based and packet-switched communication architectures. We also integrate our models into the COSI-OCC system-level communication synthesis tool and show that the more accurate modeling significantly affects optimal/achievable architectures that are synthesized by the system-level tool. Finally, this paper reviews our relevant contributions in.