Title :
Design of high-performance unified motion estimation IP for H.264/MPEG-4 video CODEC
Author :
Chun, Dongyeob ; Kim, Joonho ; Lee, Seonyoung ; Cho, Kyeongsoon
Author_Institution :
Dept. of Electron. & Inf. Eng., Hankuk Univ. of Foreign Studies, Yongin
Abstract :
Motion estimation for H.264/MPEG-4 video CODEC is very complex and requires a huge amount of computational effors because it uses multiple reference frames and variable block sizes. This paper describes the architecture and design of high-performance unified motion estimation IP based on fast algorithms for multiple reference frame selection, block matching with variable search window, block mode decision, and motion vector estimation. We described the RTL circuit in Verilog HDL and synthesized the gate-level circuit using 130nm standard cell library. The resultant circuit consists of 77,600 logic gates and 4 32times8times32-bit dual-port SRAM´s. It has the maximum operating frequency of 161MHz and can process up to 51 D1 (720times480) color image frames per second.
Keywords :
SRAM chips; hardware description languages; logic gates; motion estimation; video codecs; video coding; H.264/MPEG-4 video CODEC; RTL circuit; Verilog HDL; block matching; block mode decision; dual-port SRAM; gate-level circuit; logic gates; motion vector estimation; multiple reference frames; size 130 nm; standard cell library; unified motion estimation IP; variable block sizes; variable search window; Algorithm design and analysis; Circuit synthesis; Computer architecture; Hardware design languages; Libraries; Logic circuits; Logic gates; MPEG 4 Standard; Motion estimation; Video codecs; Block Mode Decision; H.264; MPEG-4; MV Estimation; Motion Estimation; NTSS; Reference Frame Selection;
Conference_Titel :
SoC Design Conference, 2008. ISOCC '08. International
Conference_Location :
Busan
Print_ISBN :
978-1-4244-2598-3
Electronic_ISBN :
978-1-4244-2599-0
DOI :
10.1109/SOCDC.2008.4815596
